ASIC Design and Synthesis

Name: ASIC Design and Synthesis
Brand: Springer Verlag, Singapore
SKU: 9789813346444
Price: 3125 CZK
Availability: InStock

RTL Design Using Verilog

Autor: Vaibbhav Taraate

Jazyk:

Vazba: Brožovaná

Vydavatel: Springer Verlag, Singapore

Dostupnost: Skladem u dodavatele

Odesíláme za 5-8 dnů

3 125 Kč

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a s...

Informace o knize

Autor

Vaibbhav Taraate

Jazyk

Angličtina

Vazba

Kniha - Brožovaná

Vydáno

2022

Stránek

330

EAN

9789813346444

Enbook ID

38574120

Vydavatel

Springer Verlag, Singapore

Hmotnost

539

Rozměry

155 x 235 x 20

Kompletní popis

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

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ASIC Design and Synthesis

RTL Design Using Verilog

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Kompletní popis

Mohlo by vás zajímat

Zákaznicí kteří koupili tuto knihu koupili také