Více než 4 miliony titulů v angličtině i dalších jazycích! Objevte svůj nový příběh ještě dnes!

Formal Equivalence Checking and Design Debugging

Name: Formal Equivalence Checking and Design Debugging
Brand: Springer-Verlag New York Inc.
SKU: 9781461376064
Price: 4111 CZK
Availability: InStock

Autor: Shi-Yu Huang, Kwang-Ting (Tim) Cheng

Jazyk:

Vazba: Brožovaná

Vydavatel: Springer-Verlag New York Inc.

Dostupnost: Skladem u dodavatele

Odesíláme za 5-8 dnů

4 111 Kč

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: log...

Informace o knize

Autor

Shi-Yu Huang, Kwang-Ting (Tim) Cheng

Jazyk

Angličtina

Vazba

Kniha - Brožovaná

Vydáno

2012

Stránek

229

EAN

9781461376064

ISBN

1461376068

Enbook ID

06796998

Vydavatel

Springer-Verlag New York Inc.

Hmotnost

391

Rozměry

155 x 235 x 14

Kompletní popis

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. §The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. §From the Foreword: §`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley

Nejčastěji hledané

Categories

Authors

Publishers

Produkty

Produkty

Nejčastěji hledané

Categories

Authors

Publishers

Produkty

Produkty

Formal Equivalence Checking and Design Debugging

Informace o knize

Kompletní popis

Mohlo by vás zajímat

Women's Health and Menopause

Modelling Human Behaviour in Landscapes

Differing Abilities and the Library: Fostering Equity for Patrons and Staff with Disabilities

INTERNETWORKING

Monster and the Beast, Vol. 3

Bertram Cope's Year

Dartist

Supporting Numeracy

History of Education in Europe

British Monopolies Commission

Pilgrimage

Sufi Teachings

PORTRAIT OF AN IMAGINARY MOTHER TPB

Heart, we will forget him!

How to Good-Bye Depression

Education for Self-transformation

Zákaznicí kteří koupili tuto knihu koupili také

Miracle Arrive En La Ville de Bonnye-Sur-Loire, Sous l'Eveche d'Auxerre,

Horen & verstehen ohne Probleme

Mushishi - Tome 3

Verwaltung und Bildung von Garantiekapital für die Governance

Malbec mon amour

Potencialidades futuras de la educación híbrida