Kniha Formal Semantics and Proof Techniques for Optimizing VHDL Models Kothanda Umamageswaran

Formal Semantics and Proof Techniques for Optimizing VHDL Models

Jazyk: Angličtina
Vazba: Brožovaná
Dostupnost: Skladem u dodavatele
Odesíláme za 5-8 dnů
2 286
Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifyi...

Informace o knize

Jazyk
Angličtina
Vazba
Kniha - Brožovaná
Vydáno
1998
Stránek
158
EAN
9781461373315
ISBN
146137331X
Enbook ID
06796876
Hmotnost
290
Rozměry
155 x 235 x 11

Kompletní popis

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

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