FPGA Implementation of MPEG-2 Video decoder

Name: FPGA Implementation of MPEG-2 Video decoder
Brand: VDM Verlag
SKU: 9783639295924
Price: 1149 CZK
Availability: InStock

Autor: Jiwesh Kumar, Pranjal Pandey

Jazyk:

Vazba: Brožovaná

Vydavatel: VDM Verlag

Dostupnost: Skladem u dodavatele

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The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work i...

Informace o knize

Autor

Jiwesh Kumar, Pranjal Pandey

Jazyk

Angličtina

Vazba

Kniha - Brožovaná

Vydáno

2010

Stránek

EAN

9783639295924

ISBN

3639295927

Enbook ID

06836647

Vydavatel

VDM Verlag

Hmotnost

118

Rozměry

152 x 229 x 4

Kompletní popis

The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 university program" board.

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FPGA Implementation of MPEG-2 Video decoder

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