Introduction to Systemverilog

Name: Introduction to Systemverilog
Brand: Springer
SKU: 9783030713188
Price: 3125 CZK
Availability: InStock

Autor: Ashok B. Mehta

Jazyk:

Vazba: Pevná

Vydavatel: Springer

Dostupnost: Skladem u dodavatele

Odesíláme za 10-13 dnů

3 125 Kč

This book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVer...

Informace o knize

Autor

Ashok B. Mehta

Jazyk

Angličtina

Vazba

Kniha - Pevná

Vydáno

2021

Stránek

852

EAN

9783030713188

ISBN

3030713180

Enbook ID

37628631

Vydavatel

Springer

Hmotnost

1586

Rozměry

203 x 239 x 46

Kompletní popis

This book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs.

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