Logic Synthesis and Verification Algorithms

Name: Logic Synthesis and Verification Algorithms
Brand: Springer-Verlag New York Inc.
SKU: 9781475770360
Price: 2130 CZK
Availability: InStock

Autor: Gary D. Hachtel, Fabio Somenzi

Jazyk:

Vazba: Brožovaná

Vydavatel: Springer-Verlag New York Inc.

Dostupnost: Skladem u dodavatele

Odesíláme za 10-18 dnů

2 130 Kč

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthes...

Informace o knize

Autor

Gary D. Hachtel, Fabio Somenzi

Jazyk

Angličtina

Vazba

Kniha - Brožovaná

Vydáno

2013

Stránek

564

EAN

9781475770360

ISBN

1475770367

Enbook ID

02181673

Vydavatel

Springer-Verlag New York Inc.

Hmotnost

1126

Rozměry

178 x 254 x 33

Kompletní popis

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. §Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. §A unique feature of this text is the large collection of solved problems. §Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

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Logic Synthesis and Verification Algorithms

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