Kniha Low Power and Process Variation Aware SRAM and Cache Design Avesta Sasan

Low Power and Process Variation Aware SRAM and Cache Design

Autor: Avesta Sasan
Jazyk: Angličtina
Vazba: Pevná
Vydavatel: Springer
Dostupnost: 50 % šance
Prohledáme celý svět
3 207
This book addresses process variability and power management for embedded memories, which are becomi...

Informace o knize

Autor
Jazyk
Angličtina
Vazba
Kniha - Pevná
Vydáno
2013
Stránek
200
EAN
9781461422716
ISBN
146142271X
Enbook ID
01255548
Vydavatel
Rozměry
155 x 235

Kompletní popis

This book addresses process variability and power management for embedded memories, which are becoming dominant components in today s Systems on Chip (SoCs). It provides thorough background on voltage scaling and the reliability effects on memories, while describing memory behavior at different voltages and frequencies. The authors describe a cross-layer approach, simultaneously targeting the manufacturing of devices, the inner-design of the memory circuits, as well as the way they are architected into a system. This approach enables the design of reliable, power-efficient systems in which memories are dominating area, power, and performance.

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