SATH: Simulated Annealing C code To FPGA Hardware compiler
Customizing Pipelined Simulated Annealing IP cores with a dedicated C to FPGA compiler
Autor:
Jonathan Phillips
Dostupnost:
U nakladatele na objednávku
Odesíláme za 17-27 dnů
1 407
Kč
A tool flow is presented for deriving accelerator§circuits on an FPGA §from ANSI C source code by ex...
