Static Timing Analysis for Nanometer Designs

Name: Static Timing Analysis for Nanometer Designs
Brand: Springer-Verlag New York Inc.
SKU: 9780387938196
Price: 5860 CZK
Availability: InStock

A Practical Approach

Autor: J. Bhasker, Rakesh Chadha

Jazyk:

Vazba: Pevná

Vydavatel: Springer-Verlag New York Inc.

Dostupnost: Skladem u dodavatele

Odesíláme za 10-18 dnů

5 860 Kč

The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, d...

Informace o knize

Autor

J. Bhasker, Rakesh Chadha

Jazyk

Angličtina

Vazba

Kniha - Pevná

Vydáno

2009

Stránek

572

EAN

9780387938196

ISBN

0387938192

Enbook ID

01383926

Vydavatel

Springer-Verlag New York Inc.

Hmotnost

2210

Rozměry

155 x 235 x 40

Kompletní popis

The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts.§The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology.§This book addresses CMOS logic gates, cell library, timing arcs, waveform slew, cell capacitance, timing modeling, interconnect parasitics and coupling, pre- and post-layout interconnect modeling, delay calculation, specification of timing constraints for analysis of internal paths as well as IO interfaces. Advanced modeling and analysis concepts such as controlled current source timing and noise models for nanometer technologies, power modeling including active and leakage power, crosstalk timing and crosstalk glitch calculation, verification of half-cycle and multi-cycle paths, false paths, synchronous interfaces are also covered.

Mohlo by vás zajímat

Zákaznicí kteří koupili tuto knihu koupili také

Nejčastěji hledané

Categories

Authors

Publishers

Produkty

Produkty

Nejčastěji hledané

Categories

Authors

Publishers

Produkty

Produkty

Static Timing Analysis for Nanometer Designs

A Practical Approach

Informace o knize

Kompletní popis

Mohlo by vás zajímat

Zákaznicí kteří koupili tuto knihu koupili také