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Timed Boolean Functions

Name: Timed Boolean Functions
Brand: Springer-Verlag New York Inc.
SKU: 9781461361565
Price: 2567 CZK
Availability: InStock

A Unified Formalism for Exact Timing Analysis

Autor: William K.C. Lam, Robert K. Brayton

Jazyk:

Vazba: Brožovaná

Vydavatel: Springer-Verlag New York Inc.

Dostupnost: Skladem u dodavatele v malém množství

Odesíláme za 13-18 dnů

2 567 Kč

Timing research in high performance VLSI systems has advanced at a steady pace over the last few yea...

Informace o knize

Autor

William K.C. Lam, Robert K. Brayton

Jazyk

Angličtina

Vazba

Kniha - Brožovaná

Vydáno

2012

Stránek

273

EAN

9781461361565

ISBN

1461361567

Enbook ID

06796565

Vydavatel

Springer-Verlag New York Inc.

Hmotnost

462

Rozměry

155 x 235 x 17

Kompletní popis

Timing research in high performance VLSI systems has advanced at a steady pace over the last few years, while tools, especially theoretical mechanisms, lag behind. Much present timing research relies heavily on timing diagrams, which, although intuitive, are inadequate for analysis of large designs with many parameters. Further, timing diagrams offer only approximations, not exact solutions, to many timing problems and provide little insight in the cases where temporal properties of a design interact intricately with the design's logical functionalities. This book presents a methodology for timing research which facilitates analy sis and design of circuits and systems in a unified temporal and logical domain. In the first part, we introduce an algebraic representation formalism, Timed Boolean Functions (TBF's), which integrates both logical and timing informa tion of digital circuits and systems into a single formalism. We also give a canonical form, TBF BDD's, for them, which can be used for efficient ma nipulation. In the second part, we apply Timed Boolean Functions to three problems in timing research, for which exact solutions are obtained for the first time: 1. computing the exact delays of combinational circuits and the minimum cycle times of finite state machines, 2. analysis and synthesis of wavepipelining circuits, a high speed architecture for which precise timing relations between signals are essential for correct operations, 3. verification of circuit and system performance and coverage of delay faults by testing.