Kniha Verilog by Example Blaine Readler

Verilog by Example

A Concise Introduction for FPGA Design

Jazyk: Angličtina
Vazba: Brožovaná
Vydavatel: Full ARC Press
Dostupnost: Skladem u dodavatele
Odesíláme za 9-15 dnů
476
A practical primer for the student and practicing engineer already familiar with the basics of digit...

Informace o knize

Jazyk
Angličtina
Vazba
Kniha - Brožovaná
Vydáno
2011
Stránek
124
EAN
9780983497301
ISBN
9780983497301
Enbook ID
07434756
Vydavatel
Hmotnost
202
Rozměry
154 x 227 x 8

Kompletní popis

A practical primer for the student and practicing engineer already familiar with the basics of digital design, the reference develops a working grasp of the verilog hardware description language step-by-step using easy-to-understand examples. Starting with a simple but workable design sample, increasingly more complex fundamentals of the language are introduced until all major features of verilog are brought to light. Included in the coverage are state machines, modular design, FPGA-based memories, clock management, specialized I/O, and an introduction to techniques of simulation. The goal is to prepare the reader to design real-world FPGA solutions. All the sample code used in the book is available online. What Strunk and White did for the English language with "The Elements of Style," VERILOG BY EXAMPLE does for FPGA design.

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